The present invention relates to a voltage transfer circuit and a booster circuit included in a semiconductor device such as an IC card or the like, particularly, to a booster circuit having high booster efficiency.
A non-volatile memory such as a flash memory or an EEPROM, or a dynamic semiconductor memory is internally provided with a booster circuit, and a power source. voltage supplied from an external device is boosted to generate a high voltage of a positive or negative polarity.
In general, a booster circuit consists of a capacitor and a diode element. An example of a conventional booster circuit is shown in FIG. 1. In the example, two diodes D1 and D2 are connected in series. An anode terminal of the diode element D1 in the first stage is connected to a node of a power source voltage VDD of a positive polarity, while a cathode terminal thereof is connected with a terminal of a capacitor C. Another terminal of the capacitor C is supplied with a clock signal CLK. Meanwhile, an anode terminal of the diode D2 in the second stage is connected with a cathode terminal of the diode D1 in the first stage, and a cathode terminal of the diode D2 is used as an output.
Next, operation of a booster circuit constructed in a structure as described above will be explained with reference to a waveform chart shown in FIG. 2.
Suppose that a clock signal CLK is of a ground (GND)level (or logic 0 level). The voltage of a node A of a cathode terminal of the diode D1 in the first stage is decided by VDD-VF since the anode terminal is connected to a node of a power source voltage VDD. VF denotes a forward voltage of the diode. In addition, the output, i.e., the voltage of the cathode terminal of the diode D2 is decided by VDD-2 VF, decreased by VF from the above-mentioned voltage.
When the clock signal CLK goes to a VDD level (or logic 1 level), the voltage of the node A of the A cathode terminal of the diode D1 in the first stage is increased by a differential voltage VDD since the clock signal CLX supplied to the capacitor C is changed from the GVD to the VDD, i.e., VDD-VF+VDD=2 VDD-VF. Here, the voltage of the output terminal is decided by 2 VDD-2 VF.
Further, when the clock signal CLK goes to a GND level, the voltage of the node A of the cathode terminal of the diode D1 in the first stage returns again to VDD-VF. In this state, the voltage of the cathode terminal (or output) of the diode D2 in the second stage has just been 2 VDD-2 VF, so that the voltage of the anode terminal is higher than the voltage of the cathode terminal. Specifically, the diode D2 in the second stage is brought into a reverse bias state, so that no electric charges move. Therefore, the boosted output maintains a voltage of 2 VDD-2 VF. In general, VF is about 0.6V, and therefore, the boosted output voltage is 5.4V when VDD=3.3V is chosen. This means that a boosted voltage of 5.4V is obtained from a power source voltage of 3.3V.
In practice, an output of a booster circuit normally has a charge capacitance which is much greater than that of a capacitor C in a booster circuit. A boost output terminal has a parasitic leakage current path which causes a slight leakage current to flow from a boosted voltage. If no charge is supplied from the anode terminal side of the diode D2 in the second stage, charges stored in the charge capacitance flows through the leakage current path, the boosted voltage decreases with the lapse of time. The decrease of the boosted voltage is shown in FIG. 2.
Next, when the clock signal CLK goes to a VDD level again, the boosted output voltage is increased to 2 VDD-2 VF.
A conventional circuit shown in FIG. 1 is capable of achieving the same functions even if the diode is replaced with an N-channel MOS transistor (which will be referred to as only an NMOS transistor hereinafter). For example, if a gate terminal of an NMOS transistor is connected to its own source terminal, a characteristic similar to a diode is obtained since the source terminal serves as an anode terminal and the drain terminal serves as a cathode terminal. In this case, a voltage corresponding to a forward voltage VD of the diode is VthN. FIG. 3 shows another example of a conventional booster circuit in which diodes D1 and D2 in the conventional circuit shown in FIG. 1 are replaced with NMOS transistors N31 and N32 each having a gate terminal connected with a source terminal.
In a conventional circuit using a diode shown in FIG. 1, the boosted voltage is 2 VDD-2 VF at most, as described above. In other words, the maximum boosted voltage is a value smaller than 2 VDD by 2 VF. In case of a circuit shown in FIG. 3 in which diodes are replaced with NMOS transistors, the maximum value of the boosted voltage is 2 VDD-2 VthN and is thus a value smaller than 2 VDD by 2 VthN. Thus, conventional circuits cannot avoid decreases in voltage as described above and therefore achieve a low boost efficiency.
As described above, a conventional circuit causes a problem as follow because of its insufficient boost efficiency. For example, a non-volatile memory requires a ten times higher voltage (15V) than a power source voltage VDD (1.5V) supplied from outside. In this case, booster circuits each shown in FIG. 3 are cascade-connected with each other in a plurality of stages, as shown in FIG. 4, to obtain a desired boosted voltage. Fore example, where an NMOS transistor having a threshold voltage VthN of 0.7V is used, twenty stages are required. If the number of stages is thus increased, the occupation area of the booster circuits must be increased and is very disadvantageous for an integrated circuit. The current consumption increases as the number of capacitors for supplying clock signals increases, and therefore, the performance is deteriorated in view of the purpose of low power consumption use such as a battery-driven device or the like.